1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, a fabricating method thereof and an operation method thereof. In more detail, the present invention relates to a nonvolatile semiconductor memory device that has a floating gate and is electrically rewritable, a fabricating method thereof and an operation method thereof.
2. Description of the Related Art
As the existing technology, a configuration (a single source and drain configuration) such as shown in FIGS. 1A and 1B is known. In the figures, reference numerals 1, 2A, 2B, 4, 5, 7A, BL and WL, respectively, denote a semiconductor substrate, a drain diffusion region, a source diffusion region, a floating gate, an oxide film for element isolation, a control gate line, a bit line and a word line. In this configuration, since a pair of impurity regions is necessary for each of cells adjacent in a channel length direction, there is a problem in that an area of the cell becomes larger.
In view of the above problem, there has been proposed a nonvolatile semiconductor memory device that uses a virtual ground array structure and is called an ACT (Asymmetrical Contactless Transistor) type flash memory (U.S. Pat. No. 5,877,054). A sectional view and an array architecture of the memory are shown in FIGS. 2A and 2B.
The ACT type memory cell has an n-channel transistor structure that includes source diffusion regions 2B1 and 2B2 where an impurity is lightly doped, drain diffusion regions 2A1 and 2A2 where an impurity is heavily doped, and a floating gate 4, and a control gate line 7A that works as a word line on the floating gate 4. The array configuration takes, as shown in a configuration diagram in FIG. 2B, a virtual ground structure where a source diffusion region 2B1 and a drain diffusion region 2A1 are shared in common as one impurity diffusion region. An asymmetrical distribution of the impurity concentration in the source and drain diffusion region allows having a simple virtual ground structure in which an FN tunnel phenomenon can be utilized in both write and erase operations. Furthermore, the memory cells are element-isolated between adjacent word lines only by use of PN isolation due to boron implantation, there is no need of a field oxide film. That is, the memory cell is suitable for higher integration. In the figure, reference numeral 6 denotes an ONO stacked film.
Next, a principle of operation of the ACT type memory cell will be shown. In the write operation, first, owing to the FN tunnel phenomenon on a drain side, electrons are extracted from the floating gate into the drain diffusion region, and thereby a threshold voltage is lowered. For instance, when a selected cell is written, voltages of −12 V and +4 V, respectively, are supplied to a selected control gate line and the drain diffusion region, and thereby a threshold value is lowered to in the range of from 1 V to 2 V. At this time, an electric field applied to a tunnel oxide film on an n- source diffusion region side of a non-selected adjacent cell becomes smaller than that applied to a tunnel oxide film on the drain diffusion region side of an n+ region. This is because immediately below the tunnel oxide film on the source diffusion region side having an n− region, there is a depletion layer. Accordingly, there occurs no write operation on the adjacent non-selected cells on the same control gate line. This is a reason why the write operation can be conducted by use of the FN tunnel phenomenon, and a virtual ground structure can be realized.
In the erase operation, when voltages of +10 V and −8 V, respectively, are supplied to the selected control gate line and a semiconductor substrate/impurity diffusion layer, because of the FN tunnel phenomenon of a channel region, electrons are injected from the semiconductor substrate into the floating gate, and thereby the threshold voltage is raised to 4 V or more. The erase operation can be conducted for each block and for each control gate line.
In the read operation, a control gate line voltage, a drain voltage and a source voltage, respectively, are set at +3 V, +1 V and 0 V, and whether a selected cell is in a write state or in an erase state is determined according to whether a cell current flows or not.
In FIGS. 2A and 2B, since owing to the asymmetrical source and drain structure, the impurity concentration in the bit line is necessarily divided into an n− region and an n+ region, there is a difficulty in fabrication in comparison with a single source and drain configuration.
At the time of writing, when electrons are extracted from the floating gate into the drain diffusion region side by use of the FN tunnel phenomenon, because of an inter-band tunnel phenomenon, electron-hole pairs are generated. Subsequently, part of holes that flow into the semiconductor substrate, after being accelerated by a depletion layer and obtaining a large energy, is pulled by an electric field (minus potential of the floating gate) in a longitudinal direction and captured by the tunnel oxide film. Because of this capture, the tunnel oxide film is deteriorated, and thereby endurance characteristics and reliability of data storage characteristics are deteriorated. Accordingly, there is a problem -in that when high-speed write operation is conducted, the high reliability cannot be maintained.
Furthermore, there is another problem in that since the read characteristics are largely influenced through the adjacent cells by a leakage current in a transversal direction, it is difficult to obtain a tight threshold value distribution, that is, multi-value storage is difficult.
Still furthermore, as another nonvolatile semiconductor memory device, there is proposed a configuration in which, as shown in FIGS. 3A and 3B, a control gate as a word line is divided into two and disposed in parallel on a floating gate (corresponds to 7A1 and 7A2 in the figure) (Japanese Unexamined Patent Publication No. HEI 7(1995)-312394). However, since two control gates are disposed in parallel on the floating gate with a second gate insulating film interposed therebetween, there is a problem in that a cell area becomes larger, resulting in difficulty in realizing higher integration.